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cwacsHighIngEFCI0Discard
cwacs High Ing EFCI0 Discard
1.3.6.1.4.1.351.150.2.1.1.1.1.56
The number of valid UPC/PCR parameter compliant EFCI=0 cells in the ingress direction of this Channel that are discarded at the CoS queue. This counter carries upper 32-bits of cwacsHCIngEFCI0Discard. The lower 32-bits will be present in cwacsIngEFCI0Discard.
Back to CISCO-WAN-ATM-CONN-STAT-MIB MIB page.
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